1. Field of the Invention
The present invention relates to a level shift circuit, and in particular to a level shift circuit with faster output level switching, and a method for the same.
2. Description of the Related Art
A power control circuit chip often requires a level shift circuit to convert one DC voltage level to another. The conversion may increase the voltage difference between the high and low levels, decrease the voltage difference between the high and low levels, or shift the high and low levels to different voltages without changing the voltage difference between them. FIGS. 1-3 respectively show three examples:
The circuit of FIG. 1 converts VS1/0V (high/low level of an input signal) to VS2/0V (high/low level of an output signal), and usually VS2>VS1. VS1 and VS2 for example may be 1.5V and 3.3V, respectively. Sometimes the circuit is also used in the case where VS2<VS1. The low level of the input signal and that of the output signal are the same in this circuit.
The circuit of FIG. 2 converts VS1/0V (high/low level of an input signal) to VS1/VG2 (high/low level of an output signal), wherein 0V>VG2, VG2 being −3.3V, for example. The high level of the input signal and that of the output signal are the same in this circuit.
The circuit of FIG. 3 converts VS1/0V (high/low level of an input signal) to VS2/VG2 (high/low level of an output signal), wherein VS2>VS1, and VS2>VG2. This circuit shifts both the high and low levels, and it can increase or decrease the voltage difference between the high and low levels. VS1, VS2 and VG2 are, e.g., 1.5V, 3.3V and 1.8V, respectively. The high and low levels of the output signal are both different from that of the input signal in this circuit.
All the above-mentioned prior art circuits have a common drawback: their output level switching speed is slow. Taking the circuit of FIG. 1 for example and referring to FIGS. 4 and 5, in order to ensure that the driving strength of the NMOS transistors M3 and M4 is larger than the driving strength of the corresponding PMOS transistors M1 and M2, in particular when the NMOS transistors M3 and M4 are in their worse case and the PMOS transistors M1 and M2 in their best case, the width of the NMOS transistors M3 and M4 is typically enlarged to increase their driving strength. However, this makes the driving strength of the PMOS transistor M1 weaker than that of the NMOS transistors M3, and the driving strength of the PMOS transistor M2 weaker than that of the NMOS transistors M4, resulting in the waveforms as shown in FIG. 5, wherein the time required for the output signal of the level shift circuit to switch from low to high is much slower than the time required to switch from high to low, as referring to the time points T1, T2, T3, and T4.
In the circuit of FIG. 2, the input signal IN controls the gates of the upper transistors M1 and M2, and likely, the width of the transistors M1 and M2 will also be enlarged to increase their driving strength. As a result, in this level shift circuit, the time required for the output signal to switch from high to low is much slower than the time required to switch from low to high.
In view of the foregoing drawback, the present invention proposes a level shift circuit, which is capable of speeding up the switching time of the output signal.